Non-volatile memory cells having a floating gate for the storage of charges thereon are well known in the art. Referring to FIG. 1 there is shown a cross-sectional view of a non-volatile memory cell 10 of the prior art. The memory cell 10 comprises a semiconductor substrate 12, of a first conductivity type, such as P type. At or near a surface of the substrate 12 is a first region 14 of a second conductivity type, such as N type. Spaced apart from the first region 14 is a second region 16 also of the second conductivity type. Between the first region 14 and the second region 16 is a channel region 18. A word line 20, made of polysilicon is positioned over a first portion of the channel region 18. The word line 20 is spaced apart from the channel region 18 by a silicon (di)oxide layer 22. Immediately adjacent to and spaced apart from the word line 20 is a floating gate 24, which is also made of polysilicon, and is positioned over a second portion of the channel region 18. The floating gate 24 is separated from the channel region 18 by another insulating layer 30, typically also of silicon (di)oxide. A coupling gate 26, also made of polysilicon is positioned over the floating gate 24 and is insulated therefrom by another insulating layer 32. On another side of the floating gate 24, and spaced apart therefrom, is an erase gate 28, also made of polysilicon. The erase gate 28 is positioned over the second region 16 and is insulated therefrom. The erase gate 28 is also immediately adjacent to but spaced apart from the coupling gate 26 and is to another side of the coupling gate 26. The erase gate 28 has a slight overhang over the floating gate 24. In the operation of the memory cell 10, charges stored on the floating gate 24 (or the absence of charges on the floating gate 24) control the flow of current between the first region 14 and the second region 16. Where the floating gate 24 has charges thereon, the floating gate 24 is programmed. Where the floating gate 24 does not have charges thereon, the floating gate 24 is erased. The memory cell 10 is fully disclosed in U.S. Pat. No. 7,868,375 and in U.S. Pat. No. 6,747,310 whose disclosures are incorporated herein in their entirety by reference.
The memory cell 10 operates as follows. During the programming operation, when charges are stored on the floating gate 24, a first positive voltage in the shape of a pulse is applied to the word line 20 causing the portion of the channel region 18 under the word line 20 to be conductive. A second positive voltage, also in the shape of a pulse, is applied to the coupling gate 26. A third positive voltage, also in the shape of a pulse, is applied to the erase gate 28. A voltage differential also in the shape of a pulse, is applied between the first region 14 and the second region 16. All of the first positive voltage, second positive voltage, third positive voltage and the voltage differential are applied substantially at the same time, and terminate substantially at the same time. The electrons from the first region 14 are attracted to the positive voltage at the second region 16. As they near the floating gate 24, they experience a sudden increase in the electric field caused by the voltage applied to the coupling gate 26 and the erase gate 28, causing the charges to be injected onto the floating gate 24. Thus, programming occurs through the mechanism of hot electron injection.
During the erase operation when charges are removed from the floating gate 24, a high positive voltage is applied to the erase gate 28. A ground voltage can be applied to the coupling gate 26 and/or the word line 20. Charges on the floating gate 24 are attracted to the erase gate 28 by tunneling through the insulating layer between the floating gate 24 and the erase gate 28. In particular, the floating gate 24 may be formed with a sharp tip facing the erase gate 28, thereby facilitating the Fowler-Nordheim tunneling of electrons from the floating gate 24 through the tip and through the insulating layer between the floating gate 24 and the erase gate 28 onto the erase gate 28. As disclosed in U.S. Pat. No. 7,868,375 and U.S. Pat. No. 6,747,310, it may be beneficial to have a sharp edge or tip between the side wall of the floating gate 24 and the top surface of the floating gate 24 so that electrons may more readily tunnel from the floating gate 24 to the erase gate 28 during the erase operation.
During the read operation, a first positive voltage is applied to the word line 20 to turn on the portion of the channel region 18 beneath the word line 20. A second positive voltage is applied to the coupling gate 26. A voltage differential is applied to the first region 14 and the second region 16. If the floating gate 24 were programmed, i.e. the floating gate 24 stores electrons, then the second positive voltage applied to the coupling gate 26 is not able to overcome the negative electrons stored on the floating gate 24 and the portion of the channel region 18 beneath the floating gate 24 remains non-conductive. Thus, no current or a minimal amount of current would flow between the first region 14 and the second region 16. However, if the floating gate 24 were not programmed, i.e. the floating gate 24 remains neutral or perhaps even stores some holes, then the second positive voltage applied to the coupling gate 26 is able to cause the portion of the channel region 18 beneath the floating gate 24 to be conductive. Thus, a current would flow between the first region 14 and the second region 16.
In the prior art, memory cells 10 are arranged in a plurality of rows and columns forming an array 50. Referring to FIG. 2 there is shown a top view of the array 50 of the memory cells 10 of the prior art. The plurality of memory cells 10 are arranged so that each memory cell 10, defined by a first region 14 and its associated second region 16, and the channel region 18 therebetween extends in a column direction. Further each word line 20 extends in a row direction connecting a plurality of memory cells 10 in different columns. In addition, each coupling gate 26 also extends in a row direction connecting a plurality of memory cells 10 in different columns. Further, the erase gate 28 extends in a row direction and is shared by a pair of memory cells 10 in each column. Finally, the second region 16 extends in a row direction connecting a plurality of memory cells 10 in different columns.
Further, in the array 50 of the prior art, the coupling gates 26 are strapped. The strap consists of a metal gate line (not shown in FIG. 2, but lies above the coupling gate 26) that overlies each coupling gate line 26 and is insulated therefrom. Periodically, a contact 52 electrically connects the metal gate line to the associated coupling gate line 26. In the prior art, the contacts 52 are made every 128 columns for each row of memory cells 10, as shown in FIG. 2. The creation of contacts 52 or strapping points can cause potential process margin problems. In particular, because the contacts 52 are located at the same location (in the column direction, albeit in different rows), the minimum separation 54 of the contacts 52 is reduced. (it should be noted that the there is no encroachment on the erase gate 28 by the contacts 52 as they are in different planes.). The reduction in minimum separation 54 between the contacts 52 can cause a reduction in process margin, i.e. margin of error for process deviation is decreased. This can result in less yield.
Hence, it is one objective of the present invention to increase the process margin.